FIG. 1 illustrates a prior art packet processor 100. The packet processor 100 includes a receive direct memory access (RDMA) 102 block. Direct memory access refers to a hardware subsystem that accesses system memory independently of a central processing unit. The RDMA 102 loads packets into packet memory (PM) 104. The RDMA 102 also passes a set of control information, referred to as a descriptor, to a header processor (HP). The descriptor is subsequently passed to a transmit queue (TQ) 108, which coordinates the transmittal of outgoing packets through a transmit direct memory access (TDMA) 110 block. The TDMA retrieves packets from PM 104.
The HP 106 makes decisions on what to do with the packet. Exemplary operations performed by the HP 106 include specifying an outgoing port to which a packet needs to be sent, whether a packet needs to be dropped, what modifications are needed on the packet, and whether the packet needs to be replicated. The HP 106 usually inspects and potentially modifies the first part of the packet (called the header) and does not inspect or modify the rest of the packet (called body or payload). The HP 106 usually accesses the PM 104 to read the header of the packet, and potentially writes it back modified. The processed header can have a different size than the original header (i.e., the processed header can grow or shrink in size).
The TQ 108 is a queuing system that makes decisions on when to send packets out, perform any replication of packets, respond to congestion by dropping packets, and guarantees per-flow ordering of packets.
The descriptor contains information about the packet. In particular, it contains a starting address in the PM where the packet resides. This information is generated by the RDMA (since this block stores the packet in the PM), and it is needed by the both the HP 106 (to know where the packet starts so the header can be read/written) and the TDMA 110 (so it can retrieve the packet from the PM and send it out). The HP 106 populates some information of the packet descriptor that the TQ 108 needs for its queuing decisions, and sends it to the TQ when the processing is completed. The TQ 108 sends the descriptor to the TDMA 110 after the packet is fully processed.
With the packet processor 100 of FIG. 1, the HP 106 cannot start processing the packet until the relevant portion of the packet (the header) is stored in the PM 104. The PM 104 could conservatively wait until the entire packet has been stored into the packet buffer or start processing the packet when a certain number of bytes have been stored. In either case, the HP 106 needs to wait until at least a portion of the header is stored in PM 104. This adds to the latency of the packet in the device, especially for short packets where most or the entire packet is a header.
In view of the foregoing, it would be desirable to provide a more efficient packet processor.